1. Field of the Invention
The present invention relates to signal detection in a communication system, and, in particular, to signal detection using noise prediction.
2. Description of the Related Art
Digital communication receivers sample an analog waveform and then detect the transmitted data from the sampled waveform. FIG. 1 shows a block diagram of a type of communication system 100 termed a generic SERDES (serializer/deserializer) communication channel, where impairments added in the channel are due to characteristics of a physical transmission medium for the channel, such as a backplane. In a primary channel 150, data u(n) at a transmitter is modulated by modulator 101. Modulator 101 employs modulation, such as non-return to zero (NRZ) or pulse amplitude modulation (PAM), to generate a modulated data signal a(n). The modulated data a(n) is then transmitted through backplane channel 103 after pre-equalization or pre-filtering through a transmit FIR filter (TXFIR) 102. After passing through backplane channel 103, the analog signal a(n) might be filtered by the receiver's equalizer (RXEQ) 104 which might include a continuous time filter (shown in FIG. 1 as an analog equalizer or “AEQ”). The analog signal y(t) provided by RXEQ 104 is sampled by sampler 105 at the baud rate based on a CDR sampling clock generated by a clock/data recovery (CDR) circuit (not shown in FIG. 1) to generated samples y(n).
The phase of the analog waveform applied to RXEQ 104 is typically unknown and might include a frequency/phase offset between the frequency at which the original data was transmitted and the nominal receiver's sampling clock frequency of the CDR circuit.
The CDR circuit desirably causes sampling of the analog waveform y(t) such that when the sampled waveform y(n) is passed through a data detector 106, the data is recovered properly despite that the phase/frequency of the analog waveform y(t) is not known. The CDR circuit is often implemented as an adaptive feedback circuit and the feedback loop adjusts the phase and frequency of the nominal clock to produce a modified clock, termed a recovered clock, employed by sampler 105.
After sampling y(t) to produce sampled output y(n)=y(nT), where T is the sampling and baud period, data detector 106 generates an estimate â(n) of the original modulated data a(n). Data detector 106 might be implemented as a simple slicer (a decision device based on an amplitude threshold) or a more complicated detector, such as a sequence or Viterbi detector. For high-speed applications, data detector 106 is often implemented as a slicer that is also clocked by the CDR sampling clock signal from the CDR circuit. The slicer quantizes the values of y(n) to a binary “1” or “0” based on the sampled analog value y(n) and a slicer threshold st. The slicer threshold st might typically be 0, as indicated in FIG. 1. If the input to the slicer at sampling moment n is w(n) (which, for FIG. 1, might be equivalent to y(n)), then the output value â(n) of the slicer is given as follows in equation (1), where the logic “1” and “0” are represented as corresponding signed values “1” and “−1”:
                                          a            ^                    ⁡                      (            n            )                          =                  {                                                                      1                  ,                                                                                                  if                    ⁢                                                                                  ⁢                                          w                      ⁡                                              (                        n                        )                                                                              >                                      s                    t                                                                                                                                            -                    1                                    ,                                                            otherwise                                                                        (        1        )            The estimates â(n) of the original modulated data a(n) are applied to demodulator 107 which demodulates the estimates â(n) to generate estimates û(n) of the original data u(n).
Several other impairment sources are also shown in FIG. 1. The left side of FIG. 1 shows a number of cross-talk paths 151(1) though 151(Nx) whose individual path outputs sum to create an overall cross-talk impairment signal v(t) added to the signal path of primary channel 150. Also shown in FIG. 1 is additive noise n(t) that might arise during processing within RXEQ 104 (e.g., n(t) is self-noise or output-referred noise of the AEQ). Although the figures herein each show the pre-filtering in the cross-talk paths with filters TXFIR 153(1) though TXFIR 153(Nx) similar to TXFIR 102 of primary channel 150, this is not necessarily the case in practice and does not affect the analysis herein.
As data rates increase for a particular SERDES channel application, the SERDES channel's performance degrades. Consequently, many SERDES channel applications use a decision feedback equalizer (DFE) at the receiver in conjunction with the pre-equalization through the transmit FIR filter (TXFIR).
FIG. 2 shows a block diagram of a SERDES system 200 such as discussed above with respect to FIG. 1 incorporating a traditional DFE 108. A correction, z(n), generated by DFE 108 is subtracted in combiner 109 from the signal, y(n), from sampler 105 to produce signal w(n) as given by equation (2):w(n)=y(n)−z(n).  (2)The output z(n) of DFE 108 is given by equation (3):z(n)=Σl=1Lb(l)â(n−l),  (3)where b(l) represents the coefficients of the L-tap DFE.
From equation (3), DFE 108 receives as its input the past L-modulated data estimates (also referred to herein as “decisions”) from data detector 106 ending at â(n−1). DFE filtering as given in equation (3) does not employ the current decision at â(n) so that the filtering operation of the DFE is causal. In operation, the entire DFE loop correction is desirably performed within one baud period T before the next correction is needed. In some cases, to avoid a speed bottle neck at very high data rates, a well-known technique is often employed whereby the DFE terms are pre-computed and selected based on the amplitude values of y(n). With this technique, since a DFE feedback loop is absent, the process of generating the DFE “corrected” decisions might be pipelined.
A DFE has the benefit of canceling post-cursor inter-symbol intereference (ISI) without enhancing input noise/cross-talk. However, the DFE does not directly cancel residual cross talk in the primary channel.